The use of alignment marks to properly align masks used for making a semiconductor integrated circuit during processing is well known. Alignment marks are typically depressions or high spots on the wafer surface, for example in an overlying layer, such as oxide. Often the alignment marks are covered by subsequent overlying layers. The production of alignment marks on a wafer is typically an involved process involving the exposure and etching of the alignment mark pattern in a layer overlying the silicon substrate. During the subsequent processing of the wafer, the alignment mark is typically covered with additional process layers. To align the wafer, the wafer stepper scans light, such as from a laser, on the wafer and detects any diffraction patterns generated by the underlying alignment mark. The diffraction patterns are converted into electrical signals that are analyzed by the wafer stepper, which then aligns the wafer accordingly.
There are several commonly used alignment marks types and methods for detecting the marks, including: Laser Step Alignment (“LSA”), Field Image Alignment (“FIA”), Laser Interferometric Alignment (“LIA”), and Wafer Global Alignment (“WGA”), all of which were developed by Nikon Corp. Additional alignment systems are for example, the Axiom System by Silicon Valley Group Lithography, and the system used with the Canon 6 Bar.
The diffraction patterns generated by the underlying alignment marks are a function of the size and shape of the alignment mark as well as the material and thickness of the alignment mark and any overlying layers. To improve the accuracy of the alignment system, it is desirable to optimize the diffraction patterns generated by the underlying alignment mark. To optimize a diffraction pattern produced by a specific alignment mark it is necessary to appropriately adjust the thickness and geometry of the layers.
Currently, optimization of size, shape, and depth of alignment marks is performed by physically producing the actual alignment mark on a test wafer and testing the alignment mark to determine the strength of its resulting signal. Several variations of the mark may be produced and tested on a single test wafer. For example, variations of the size or geometry of the mark may be produced on one wafer. Variations of the thicknesses of the various layers, however, are produced on separate wafers. The alignment mark with the strongest signal is then chosen as the optimized alignment mark. The actual production of alignment marks for testing, however, is expensive and involves a significant amount of valuable time on the wafer steppers, thereby reducing yield produced by the wafer steppers.
Thus, there presently is a need for a method of testing and optimizing an alignment mark without requiring the actual manufacture and testing of the mark.